Because of the specialties of the IP design, driver designer should consider the route switch between the high-speed and the full speed controller, access to shared buffer, and the mode of ARM accessing the IP core as a slave. 由于IP硬件设计的特殊性,主机控制器驱动的设计需要考虑到高速与全速控制器的路由切换与缓存区的共享,以及ARM访问作为SLAVE的IP核的方式。
By using ARM + DSP master slave system, embedded uC / OS - ⅱ and reasonable task-assigned strategy, the real-time of the system were guaranteed. 该方案通过采用ARM+DSP主从结构、嵌入式uC/OS-Ⅱ系统及合理任务分配策略保证了系统的实时性要求。
This paper introduced a method of using ARM microprocessor to configure FPGA in slave serial in embedded system. System program and configuration data were stored in Flash, the timing was generated by ARM general IO, the dedicated configuration PROM were reduced. 介绍一种在嵌入式系统中使用ARM处理器从串配置FPGA的方法,将系统程序及配置数据存储在系统Flash中,利用ARM的通用I/O口产生配置时序,省去专用的配置PROM;
In the SOC, 3 master buses are connected with DATA, INST of ARM core, and system DAM bus, and 8 slave buses are connected with some peripheral buses and external memories. 将3条主总线分别连接到ARM核的数据总线、指令总线和DMA总线,再将8条从总线连接到外围总线及外围存储器等。
The hardware of master and slave modules uses embedded ARM processor with CAN controller as their core CPU and uses the real time operating system & μ C / OS - ⅱ as their software designing platform. 主/从站硬件采用带有CAN控制器的嵌入式ARM处理器作为它们的核心,并采用μC/OS-Ⅱ嵌入式实时操作系统作为软件开发平台。