Through controlling an N-bit accumulator and then get its highest bit to generate the programmable clock. 通过控制一个N位累加器累加,取其最高位,即可得到可编程时钟(PCL)源。
The experimental result certifies that this programmable clock has many advantages, such as high precision, good stability. 实验结果验证了该时钟源具有精度高、稳定性好等优点。
Circuits for programmable clock generators 可编程的时钟发生器
Design of a high efficient programmable clock 一种高效的可编程时钟(PCL)源设计
We introduce an on - chip clock synchronous method, in which programmable delays are in - serted in the clock distribution network, such that clock alignment and synchronization are achieved. 本文介绍了一种SoC时钟同步设计方法,这种方法将可调节延时的时钟电路插入在时钟分布网络中,以取得时钟边沿的匹配和同步。