WLP ( Wafer Level Package(WLP) ), 3-D Chip Stacking and SOI ( Silicon-on-insulator ) are the three impetuses for the development of wafer bonding technology. 晶圆级封装、三维芯片堆叠和绝缘体上硅技术是推动晶圆键合技术发展的三大动力。
This paper introduces the design and usage of FEP - 1 vertical fountain plating, which is met to fabricate bumps on wafers in wafer level package. Computational simulation and optimization by finite - element analysis ( FEA ) were used in designing vertical fountain plating. 介绍了为满足微电子新颖封装&圆片级封装(WLP)在硅圆片上制作凸焊点的需要,根据有限元分析模拟优化,设计研制了FEP-1垂直喷镀机。
A Novel Package for Microelectronics : Wafer Level Package(WLP) 一种新颖的微电子封装:圆片级封装
The Research and Development of Vertical Fountain Plating for Making Bumps in Wafer Level Package(WLP) 制作圆片级封装凸焊点的垂直喷镀机研制
Current commercial vacuum gauges cannot be applied in MEMS wafer level vacuum package for their big size. 目前商用的真空规由于体积大,无法应用于体积小的圆片级MEMS真空封装中。