By reasonably using the special resources in FPGA, such as DCMs ( Digital Clock Manager(DCM) ) and BUFGMUXs ( global clock MUX buffer ) and manually building up a proper clock circuit, the interference to timing caused by clock skew is mostly reduced. 通过合理使用DCM(数字时钟管理单元)和BUFG-MUX(全局时钟选择缓冲器)等FPGA的特殊资源,手动搭建时钟电路,可以尽可能地减少时钟偏差对电路时序的影响。