Binary Addition and Subtraction, Implementation and Performance of the Full Adder(FA), High-speed Addition, Signed Arithmetic. 二进制加减,全加器的实现和性能,高速加法,带符号加法。
Design methods of one-bit full adder circuit 一位全加器实验电路设计方法的研究
Generalized Full Adder(FA) in Array Multiplier Design Model Application 一般化全加器在阵列乘法器设计中的典型应用
A Dynamic Full Adder(FA) Circuit Based on Single Electron Transistors 基于单电子晶体管的动态全加器电路设计
Functional testing of a FPGA is investigated by implementing a full adder in it. 以一位全加器为例,研究了器件的功能测试方法。