Time-to-digital converter for frequency synthesis in 0.18 μ m CMOS 0.18MCMOS中用于频率综合的时间数字转换器
A high-resolution Time-to-Digital Converter(TDC) which based on analog interpolation is introduced in this paper. 文章介绍了一种基于模拟内插技术的高分辨率时间数字变换器的设计实现。
The present research papers in the previous time-to-digital converter circuit based on the use of the FPGA to achieve high-speed time-to-digital converter circuit of a comprehensive study of detail. 本论文在调研了以前时间-数字转换电路工作的基础上,对用FPGA来实现高速时间-数字转换电路的研究进行了全面详细的介绍。
Based on the summarization of commonly used time interval measurement methods and combined with the internal structure of FPGA, a design of Time-to-Digital converter in FPGA is analyzed and verified. 通过对常用的时间间隔测量方法进行总结,在其基础上结合FPGA的内部结构,对在FPGA中实现高分辨率TDC的可能性进行了分析和验证。
In the high-performance time measurement system, the high performance time-to-digital converter chip can only be initialized and controlled by JTAG. A test bus controller is used to realize functions of JTAG. 在高性能时间测量系统中,高性能时间数字转换芯片只能通过JTAG进行初始化和控制,为此选择了TBC控制器来实现的方法。