A new design rule checking approach based on scan line algorithm for IC layout was proposed. 提出一种新的基于扫描线算法的IC版图几何设计规则检查(DRC)方法。
This paper states design of layout and examination of DRC ( Design Rule Checking(DRC) ) and LVS ( Layout Versus Schematic ) and extract of RC parasitic parameter of a kind of memory of 16 digit. 阐述了对一种16位存储器版图设计中的DRC(DesignRuleChecking)即“设计规则检查(DRC)”和LVS(LayoutVersusSchematic)即“版图和电路比较”、以及RC寄生参数的提取。
A Study on the Practicability of Hierarchical Design Rule Checking(DRC) 分级式设计规则检查(DRC)的实用化研究
Hierarchical Design Rule Checking(DRC) Approach for IC Layout 分级式IC版图设计规则检查(DRC)
For hierarchical design rule checking ( DRC ), false errors may result from inadequate graph operation or incomplete graph of the cell while the environment in which the cell is called is not considered during checking. 分级式DRC在检查时,可能因为运算不当而改变图形形状,或单元本身存在不完整的图形,检查中又未能考虑单元的调用环境而产生伪错。