Abundant flip-flop resource of FPGA made it possible to design survival path exchange register module. The solution decreased complexity of decoder control process as increased speed of decoder. 方案中设计了幸存路径交换寄存器模块,充分利用FP-GA中丰富的触发器资源,减小了译码器状态控制的复杂度,提高了VB译码器的运行速度。