The phase jitter of output signal of the PLL ( phase locked loop ) frequency doubler is analyzed. 定量分析了数字式锁相倍频器输出信号的相位抖动。
Through debugging the hardware circuit of the Phase Locked Loop(PLL) and writing the Single-Chip Processor program, a good performance frequency source is realized. 通过对锁相环(PLL)硬件电路的调试和编写相关单片机控制程序,实现了一个性能较好的频率源。
An automatic accurate synchronization control scheme which adopts phase locked loop principle is presented. 利用锁相环(PLL)路原理提出锁相自动准同期控制方案。
Design and Realization of Phase Locked Loop(PLL) under Three-phase Unbalance Voltages 三相电压不平衡条件下锁相环(PLL)的设计与实现
The operating principle and performance of fractional-N phase locked loop ( FNPLL ) are described in detail, and the methods of suppressing FNPLL phase modulation sideband are introduced. 较详细介绍了分数分频锁相环(PLL)的工作原理和特性,以及抑制分数分频锁相环(PLL)相位调制边带的方法。