Moreover, based on comparative analysis of Synopsys Design Compiler(SDC) to implement the hardware at the same constraint, an efficient half pixel interpolation filter ( 6-tap FIR ) architecture had been given finally. 并且在相同的约束条件下,使用Synopsys综合工具比较了各自的实现代价,最终给出了6阶1/2像素插值滤波器的优化实现结构。
During the synthesis level, this thesis adopts the proper synthesis strategy and optimization measure to synthesize the IP core using Synopsys's Design Compiler. 综合阶段,针对SDUM08的特点,采用合适的综合策略和优化手段,使用Synopsys公司综合工具Designcompiler对IP核进行了逻辑综合,并对综合结果进行了分析。