With the typical circuit fault model and conventional BIT testing method, this paper researches into the validation technique of BIT and smart fault detection which enhance the test effect of BIT. 本文结合数控系统典型电路故障模式和常规BIT检测方法,研究BIT的验证技术,并开展智能故障检测方法的研究,以提高BIT的检测水平。
Design verification or validation and test are significant for good functionality and reliability of Integrated Circuits ( ICs ). Sequential circuit Automatic Test Pattern Generation ( ATPG ) is then very important, but difficult as widely recognized. 集成电路(Integratedcircuit,简称IC)的设计验证与测试对保证其功能的正确性和可靠性非常重要,而时序电路测试生成则是其中一个相当困难的问题。