A sequential equivalence checking algorithm based on state transfer graph is presented. 提出一种基于状态转换图的时序电路等价验证算法。
An improved algorithm based on register mapping is proposed to increase the speed of equivalence checking for sequential circuits. 为了提高时序电路的等价性验证速度,提出一种改进的基于寄存器匹配的验证算法。
A sequential equivalence checking based approach for system level soft error reliability evaluations proposed. It's prototype tool is accomplished in C language on the VIS system. 提出了一种基于时序等价性检查技术的组合逻辑单元系统级可靠性分析理论和方法,并基于VIS系统下用C语言实现了原型工具。
Equivalence Checking(EC) between System Level Model and RTL Implementation 系统级模型与RTL实现的等价性验证方法
Logic Synthesis and Equivalence Checking(EC) of Communication Chip 一款通信芯片的逻辑综合和等价性验证