In the last decade, because of its innate parallel decode algorithm and excellent error correction performance, Low-Density Parity-Check code ( LDPC code ) have been received close attention from numerous of investigator at home and broad. 低密度奇偶校验码（LDPC码）以其自然并行的译码算法和优异的纠错性能，近十几年来受到海内外众多研究学者的极大关注。
On a comprehensive consideration of the coding-rate and complexity of hardware implementation of Turbo decoder, a high coding-rate parallel Turbo decode algorithm is designed and a controller structure applicable to different decoding algorithms is presented. 在综合考虑了Turbo译码效率和硬件实现的复杂度的基础上，设计了一种高效的并行Turbo译码算法，并且给出了一种设计较为简单，适用于不同并行译码(PD)算法的控制器结构。
With serial to parallel converter, we can decode the PCM. 用串并转换器对PCM码解码。
Design the Viterbi decoder in VHDL language, employ eight-voltage quantum soft decision and parallel structure, improve the decode speed, present information storage and management to ameliorate the traditional register exchange method. 采用VHDL语言设计了Viterbi译码器，采用八电平量化软判决和并行结构，提高了译码速度，引入信息存储和管理对传统的寄存器交换法进行改进。
The design makes the most of hardware resource Spartan-II chip, and adopts pipeline and parallel mode in order to improve the system clock and decode speed. 为充分利用Spartan-II芯片的硬件资源，编译码器采用了流水线方式与并行方式，并提高了系统时钟频率。
