Optimization of Hardware Overhead in Continuous Checksum-Based Analog Error Detection Circuit(EDC) 基于连续校验和的模拟检错电路硬件开销的优化
Design and Realization of Error Detection and Correction Circuit for Computer RAM 计算机RAM检错纠错电路的设计与实现
It is a strong error detection mechanism, it can be a good anti-jamming, greatly enhanced the stability of transmission is very suitable for automotive control. Second, it introduces the design of the hardware circuit diagram. 它强大的错误检测机制,使它能够很好的抗干扰,大大增强传输的稳定性。其次,介绍了此次设计的硬件电路图。