This paper presented the design and implementation of two sequential circuits in FPGA configurable logic block, namely, distributed RAM and shift register. 本文主要研究高性能FPGA可编程逻辑单元中分布式RAM和移位寄存器两种时序功能的设计实现方法。
A fine-grained mapping approach is proposed according to the analysis of the detailed configurable logic block structure of FPGA device, and it is applied to the design of a systolic array for modular multiplication based on FPGA. 通过分析FPGA可配置逻辑块的细致结构,提出了一种基于FPGA的细粒度映射方法,并使用该方法高效实现了大数模乘脉动阵列。
This method begins with selecting logic element ( LE ) with minimum connectivity factor as the seed of the packing, and then uses a heuristic function based on routability-driven to obtain the most appropriate LE to pack into the configurable logic block ( CLB ). 选择连接因子最小的节点作为种子节点;采用基于布通率的启发式函数来选择最合适的逻辑单元(LE)装箱到可配置逻辑单元(CLB)内部。
To incorporate the latest developments in the configurable RAM block, it has a certain amount of research on the configurable FIFO control logic that embedded in the RAM block. 本文还结合了目前可配置存储器模块的最新发展,对嵌入在可配置存储器模块中的可配置FIFO控制器进行了研究。