Real-time operating system interrupt flag; RTOSINT&实时操作系统中断标志(IF);
A design method based on multiplexing execution-cycle and interrupt flag signals using register model is proposed. S. 提出了中断执行周州复川、寄存器模型设计中断标识信号的中断电路实现方法。
This paper introduces the method of execution - cycle multiplexing and the designs of interrupt flag signals using register model in interrupt module architecture. Some control signals are illustrated with Verilog HDL design in detail. 文章介绍了一种采用中断执行周期复用、寄存器模型设计中断标识信号的中断电路实现方法,并给出了关键控制信号的Veriloghdl程序实现。
If the interrupt simulation status flag is set, return EBUSY. 如果设置了中断模拟状态标志,它就会返回EBUSY。
Once the interrupts are generated, reset the interrupt simulation status flag and return success. 中断生成之后,就重新设置中断模拟状态标志,并返回成功。