This article analyzes the principle of header error control ( HEC ) in ATM, and puts forth the hardware circuits and software implementation of HEC sequence and its error correction. 论文通过对ATM中的信头差错控制(HEC)的原理分析,提出了HEC序列产生的硬件电路和软件实现方案以及纠错的硬件电路和软件实现。
This article describes reuse based functional block design flow through developing the header error control ( HEC ) processing block set. 本文通过异步传递方式中信头差错控制(HEC)模块组的设计,阐明基于设计再利用的功能模块的设计流程。
Header error control functional blocks for design reuse 用于设计再利用的信头差错控制(HEC)模块组
Concatenated code is applied to ATM cell header as an error control solution. This paper analyzed the concatenated code combined BCH code with convolution code and concatenated code combined BCH code with Reed-Solomon ( RS ) code. 同时分别对BCH码与卷积码构成的级联码和BCH码与里德&所罗门(RS)码构成的级联码进行了研究与比较。