Comparing Automatic Test Pattern Generation(TPG) System 数字电路测试向量自动生成系统的比较
Based on cell fault model, the paper studies test pattern generation and self test of tree adder, which is frequently used in the high performance processors. 时延故障对高速运算电路性能有着关键性的影响,本文对其中之一的并行前置树型加法器的通路时延故障测试作了研究。
Test pattern generation program 测试码模式生成程序
This paper presents a test pattern generation system implemented on a CAD workstation. 本文介绍了一个在康发工作站实现的测试产生系统COMPA-ATPGS。
Therefore, the study of multi-core chip low-power BIST test pattern generation and application is of great significance. 因此研究多核芯片BIST低功耗测试模式生成(TPG)和应用,具有十分重要的意义。