Analysis and Design of A Novel Low Noise Current-Steering Logic(CSL) 一种新型低噪声电流控制逻辑的分析与设计
Using a constant biasing current and a reduced output logic swing, current-steering logic avoids the large digital switching noise of conventional static CMOS logic. 通过采用恒定工作电流和限制电路的输出逻辑摆幅,电流控制逻辑能避免静态CMOS电路工作时引入的瞬态开关噪声电流。
Novel Low Noise Current-Steering Logic(CSL) and Its Comparison With CMOS Static Logic for Mixed-Mode ICs 一种适用于模/数混合集成电路的新型低噪声电流控制逻辑